SOC Platform
Ocean Platform: Fast Forward Your Innovation
At GSOC (Generic System On Chip), we are pioneers in developing configurable SoC designs that cater to diverse industry needs. Our latest Ocean Platform brings the next generation of complex, customizable SOCs, built to accelerate your innovation journey and streamline your development process.
Main Advantages
Fast Time-to-Market
Accelerate your ASIC development with an SOC platform tailored for rapid deployment, enabling you to concentrate fully on developing your IP.
Lower Development Costs
Minimize your project expenses by leveraging a pre-built SOC framework. Common IPs and CPUs are royalty-free, offering significant savings.
Easy Customization
No need to compromise on features and performance. The Ocean Platform provides a wide range of customization options, including modular IP selection, scalable architecture, and configurable interfaces.
Platform Features
Design and Verification Duo
The Ocean Platform is uniquely built from dedicated Design and Verification sections, ensuring seamless integration and establishing it as the most complete and advanced solution for delivering exceptional end-to-end products.
Based on RISC-V CPUs
Harness the power of RISC-V architecture for cutting-edge performance and flexibility.
Optimized for Easy Selection and Replacement
Enjoy the flexibility of easily swapping components and configurations to meet your exact needs.
Why Ocean Platform
The Ocean Platform is designed to keep you ahead of the curve by offering a powerful, adaptable SoC foundation. Whether you’re working on AI, IoT, or high-performance applications, our platform supports your innovation at every step.
Ocean Sub systems
Manta
Peripheral
- USB1.1 Host
- Ethernet Controller
- Watchdog Timer
- Timer
- Internal SRAM
- Hiper RAM controller
- DMA
- AXI internal Matrix
Orca
Management
- Dual core RISC-V CPU
- I2C, UART , SPI slave
- QSPI flash control
- Boot ROM
- JTAG TAP
- GPIOX32
- Mail box
- Interrupt controller
- DMA
Seal
Safety
- Triple core RISC-V CPU
- Triple Core lock step mechanism
- Boot Rom for self safe boot up
- run RTOSs and safety-critical applications
- 128 external interrupts
Shark
Security
- Based on OpenTitan project
- Enable Secure Silicon
- Dual Core RISC-V cpu
- Enable Secure Boot
- Complete Software stack
Otter
External memory
- High BW AXI subordinate port with 128 bit data bus width
- APB slave for internal sub system configuration
- DDR controller
- QSPI controller for non-volatile memory access
- Scratch Pad Memory
- Auxiliary DMA
Dolphin
PMCA
- Programmable Many Core Accelerator specialized in accelerating the inference of Deep Learning and Machine Learning models
- 12 32-bit RISC-V cores empowered with ISA extensions, enabling integer arithmetic from 32-bit down to 2-bit precision.
Marlin
Slow interface
- 2xUART
- 2xI2c
- I3C
- SPI subordinate
- JTAG debug
- DMA
- Internal Memory
- Sub System Reg file