Driving the Chiplet Revolution: GSOC Solutions at OCP Global Summit 2025
Published by GSOC Solutions | October 2025
The semiconductor industry is undergoing a fundamental paradigm shift, moving from monolithic chip architectures toward modular, scalable chiplet-based designs. At the forefront of this transformation stands the Open Compute Project (OCP) and its Open Chiplet Economy (OCE) initiative. At the OCP Global Summit 2025, held October 13–16 in San Jose, California, GSOC Solutions CEO Itai Nadler took the stage alongside Rob Pelt of AMD and Durgesh Srivastava of DataraAI to formally introduce the OCP Chiplet Systems Workstream — a landmark effort calling the entire semiconductor industry to embrace multi-vendor interoperability.
The Challenge: Why Multi-Vendor Chiplet Integration Is Hard
The promise of chiplets is compelling: modular design, reduced time-to-market, cost efficiency, and the ability to mix and match the best components from multiple vendors. Yet the reality of integration has remained stubbornly complex. As Itai Nadler stated plainly during the presentation:
“Connecting chiplets is not an easy task, it’s not a walk in the park — it’s actually difficult.”
Today’s chiplet landscape is dominated by large companies operating with proprietary interfaces and incompatible specifications. This creates a fragmented ecosystem where integration complexity is enormous and the barrier to entry for smaller players remains prohibitively high. The Chiplet Systems Workstream was established precisely to dismantle these barriers.
The workstream’s ambition extends well beyond standardizing physical connections. As Nadler explained:
“We want to standardize not just the PHY and the link layer, but we want to standardize the upper layer of the system — from the firmware, from APIs, up to the operating system.”
This holistic, full-stack approach is what distinguishes the OCP Chiplet Systems Workstream from prior standardization efforts.
The Workstream’s Approach: Building on the OCE Ecosystem
The Chiplet Systems Workstream functions as a coordinating body within the broader OCE ecosystem. Rather than duplicating existing efforts, it builds upon the work of specialized groups covering PHY, Link Layer, CDX, Caliptra Root of Trust, D2D testing, and packaging. The System Working Group sits at the center of this network, ensuring that all individual workstreams converge into a coherent, vendor-agnostic integration framework.
“We are not inventing the wheel for everything. We rely on the huge work done by OCE… we are facilitating the work done by other groups to present a cohesive picture of how chiplets from different vendors can work together.”
— Itai Nadler, CEO, GSOC Solutions
The workstream also provides practical tooling: an easy-to-use compatibility framework (encapsulated in a structured Excel-based table) that allows developers to define their chiplet’s full parameter set and automatically match it against others to verify compatibility. Scripting tools are being developed to automate this matching process at scale.
Five Pillars of Interoperability
The Chiplet Systems Workstream has organized its technical agenda around five foundational pillars, each targeting a distinct dimension of the integration challenge.
Silicon & Systems Architecture forms the bedrock of the entire effort. The focus here is on establishing standardized interface definitions, modular system design principles, interoperability specifications, and scalable architecture frameworks — including firmware compatibility standards. The overarching goal is to create unified architectural standards that require and reward deep cross-vendor collaboration, ensuring that chiplets designed independently can be composed into coherent, functional systems.
Security Frameworks address one of the most critical and often overlooked dimensions of multi-vendor integration. The workstream is developing comprehensive threat models, inter-vendor trust mechanisms, secure boot and authentication protocols, encrypted communication standards, and supply chain security processes. The goal is unambiguous: ensure secure communication and verifiable trust across chiplets from different vendors, regardless of their origin.
Power Efficiency tackles the challenge of coordinating power management across a heterogeneous chiplet assembly. This pillar covers dynamic power management standards, cross-chiplet power coordination protocols, and thermal management frameworks. Without a common language for power negotiation and thermal signaling, multi-vendor systems risk inefficiency and instability — making standardization in this area essential for any production-grade deployment.
Performance Optimization ensures that the industry can meaningfully measure and compare chiplet performance across vendors. The workstream is defining standardized performance metrics, measurement methodologies, cross-vendor comparison frameworks, and benchmarking standards. This pillar is critical for enabling procurement decisions, system-level design trade-offs, and competitive transparency in a healthy, open chiplet marketplace.
Compatibility & Validation is the pillar that ties everything together. It provides the practical frameworks, integration checklists, certification guidelines, and testing methodologies that engineers need to verify that a multi-vendor chiplet assembly will actually work as intended. The goal is to give developers the confidence to build on open standards, knowing that a rigorous validation process stands behind every integration.
Seven Use Cases for Silicon & Systems Architecture
The workstream has defined seven concrete use cases to ground its architectural work in real-world deployment scenarios. These use cases span the full breadth of modern compute applications:
- Accelerators — AI and ML inference and training workloads
- Homogeneous Compute — Scalable multi-chiplet CPU configurations
- Networking — High-throughput, low-latency data plane chiplets
- Streaming I/O — High-bandwidth data streaming applications
- Sensor Hubs — Edge and embedded sensor aggregation platforms
- SOC Expansion — Modular expansion of existing SoC designs with specialized chiplets
Each use case is supported by detailed architectural diagrams illustrating how chiplets from different vendors can be composed into a functional system, covering 2D, 2.5D, and 3D packaging configurations.
Security at the Core: The Caliptra Reference Model
Security is a non-negotiable requirement in any multi-vendor ecosystem. The workstream’s security framework addresses the full threat surface of a heterogeneous chiplet system, including inter-vendor trust establishment, secure boot and authentication, encrypted communication protocols, and supply chain integrity. The OCP’s Caliptra project is referenced as a model for root-of-trust implementation, though the workstream maintains a vendor-agnostic stance and does not mandate its adoption.
GSOC Solutions: The Ocean Platform Is Now Chiplet Ready
GSOC Solutions is not merely advocating for standards — the company is actively building the technology to embody them. One of the most significant announcements made during the OCP Summit presentation was that the GSOC Ocean Platform is now Chiplet ready.
The Ocean Platform is a configurable, generic SoC designed to dramatically accelerate customer ASIC development. Built on a RISC-V CPU architecture and optimized for easy customization, the platform now supports chiplet integration natively. This makes it one of the first commercially available generic SoC platforms to be fully aligned with the emerging OCP chiplet interoperability standards.
| Ocean Platform Feature | Description |
|---|---|
| Architecture | Based on RISC-V CPU |
| Design Approach | Configurable Generic SoC |
| Chiplet Readiness | Fully chiplet-ready, aligned with OCP/OCE standards |
| Development Model | Design and verification duo for rapid customization |
| Optimization | Engineered for easy customer ASIC customization |
A Call to Action: Join the Chiplet Revolution
The OCP Chiplet Systems Workstream is actively seeking contributors from across the semiconductor industry. The first formal specification is targeted for release in the second half of 2026, and the window to shape that specification is open now.
GSOC Solutions is proud to co-lead this effort alongside AMD’s Rob Pelt, and we extend an open invitation to engineers, architects, IP vendors, system integrators, and technology leaders to join the workstream. The chiplet revolution is not a distant future — it is being built today, in open collaboration, one standard at a time.
Resources
- Watch the full OCP Summit presentation: YouTube — Introducing the OCP Chiplet Systems Workstream
- Download the presentation slides: Google Drive — OCP Chiplet Systems Workstream Slides
- OCP Open Chiplet Economy : OpenCompute.org — OCE