GSOC is looking for an experienced verification engineer to join our new emerging projects.
In this roll you will join one of our teams developing a SOC or an IP, using state of the art verification methodologies.
Your responsibilities will be a full cycle verification of a module – developing the verification environment, defining and executing test plans, defining and collection coverage reports.
• University degree in one of the following: electronics, communication, computer science.
• Above 3 years’ experience in functional verification with Specman or System Verilog
• Full project cycle experience: test plan, architecture, execution, regression and coverage.
• UVM methodology experience
• Verilog/VHDL knowledge
• Gate Level simulation – advantage
• Formal verification – advantage
• Design experience – advantage
• Strong interpersonal and communication skills
• Fluent in English
• Highly motivated and self-managed.